Over the last four decades the semiconductor industry has improved the performance and power consumption of integrated chips (ICs) by reducing the size of components within the ICs. For example, by reducing the size of transistors within an IC, semiconductor manufacturers are able to build ICs having more transistors that operate at faster speeds and lower power.
In large part, the ability to shrink the size of components within an IC is driven by lithographic resolution. In recent years however, tool vendors have been unable to adequately decrease the wavelength of illumination sources, so that developing technology nodes have minimum feature sizes of 20% or less than the wavelength of illumination used in lithographic tools.
Multi patterning lithography (MPL) is one lithography strategy that is used in emerging technology nodes to overcome limitations in lithographic resolution. During MPL data prep, an original layout is decomposed into two or more colors (e.g., black and gray), such that features of a same color are formed on a same mask of a multiple patterning lithography exposure (e.g., a double patterning, triple patterning, etc.). By splitting IC layout data into multiple masks, printing below a printable threshold is enabled since the data on each of the separate masks does not violate the printable threshold.